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| MOTOROLA SEMICONDUCTOR TECHNICAL DATA Low Voltage 1:10 CMOS Clock Driver The MPC946 is a low voltage CMOS, 10 output clock buffer. The 10 outputs can be configured into a standard fanout buffer or into 1X and 1/2X combinations. The ten outputs were designed and optimized to drive 50 series or parallel terminated transmission lines. With output to output skews of 350ps the MPC946 is an ideal clock distribution chip for synchronous systems which need a tight level of skew from a large number of outputs. For a similar product with more outputs consult the MPC949 data sheet. MPC946 LOW VOLTAGE 1:10 CMOS CLOCK DRIVER * * * * * * * * Clock Distribution for PentiumTM Systems with PCI 2 Selectable LVCMOS/LVTTL Clock Inputs 350ps Output to Output Skew Drives up to 20 Independent Clock Lines Maximum Input/Output Frequency of 150MHz Tristatable Outputs 32-Lead TQFP Packaging 3.3V VCC Supply With an output impedance of approximately 7, in both the HIGH and the LOW logic states, the output buffers of the MPC946 are ideal for FA SUFFIX driving series terminated transmission lines. More specifically each of the TQFP PACKAGE 10 MPC946 outputs can drive two series terminated transmission lines. CASE 873A-02 With this capability, the MPC946 has an effective fanout of 1:20 in applications using point-to-point distribution schemes. The MPC946 has the capability of generating 1X and 1/2X signals from a 1X source. The design is fully static, the signals are generated and retimed inside the chip to ensure minimal skew between the 1X and 1/2X signals. The device features selectability to allow the user to select the ratio of 1X outputs to 1/2X outputs. Two independent LVCMOS/LVTTL compatible clock inputs are available. Designers can take advantage of this feature to provide redundant clock sources or the addition of a test clock into the system design. With the TCLK_Sel input pulled HIGH the TCLK1 input is selected. All of the control inputs are LVCMOS/LVTTL compatible. The Dsel pins choose between 1X and 1/2X outputs. A LOW on the Dsel pins will select the 1X output. The MR/Tristate input will reset the internal flip flops and tristate the outputs when it is forced HIGH. The MPC946 is fully 3.3V compatible. The 32-lead TQFP package was chosen to optimize performance, board space and cost of the device. The 32-lead TQFP has a 7x7mm body size with a conservative 0.8mm pin spacing. Pentium is a trademark of Intel Corporation. 10/96 (c) Motorola, Inc. 1996 1 REV 1 MPC946 LOGIC DIAGRAM TCLK_Sel TCLK0 TCLK1 (Int Pull Down) (Int Pull Up) 0 (Int Pull Up) /1 /2 R 0 1 3 Qa0:2 1 Dsela (Int Pull Down) 0 1 Dselb (Int Pull Down) 3 Qb0:2 0 1 Dselc MR/OE (Int Pull Down) (Int Pull Down) 4 Qc0:3 Pinout: 32-Lead TQFP (Top View) GNDb GNDb VCCb VCCb VCCc Qb0 Qb1 Qb2 24 VCCa Qa2 GNDa Qa1 VCCa Qa0 GNDa MR/OE 25 26 27 28 23 22 21 20 19 18 17 16 15 14 13 Qc3 GNDc Qc2 VCCc Qc1 GNDc Qc0 VCCc FUNCTION TABLES TCLK_Sel 0 1 Dselx 0 1 MR/OE 0 1 Input TCLK0 TCLK1 Outputs 1x 1/2x Outputs Enabled Hi-Z MPC946 29 30 31 32 1 2 3 4 5 6 7 8 12 11 10 9 TCLK_Sel VCCI TCLK0 TCLK1 Dsela Dselb MOTOROLA Dselc GNDI 2 TIMING SOLUTIONS BR1333 -- Rev 6 MPC946 ABSOLUTE MAXIMUM RATINGS* Symbol VCC VI IIN TStor Supply Voltage Input Voltage Input Current Storage Temperature Range (CMOS Inputs) -40 Parameter Min -0.3 -0.3 Max 4.6 VDD + 0.3 20 125 Unit V V mA C * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied. DC CHARACTERISTICS (TA = 0 to 70C, VCC = 3.3V 0.3V) Symbol VIH VIL VOH VOL IIN ICC CIN Characteristic Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Output LOW Voltage Input Current Maximum Quiescent Supply Current Input Capacitance 70 2.5 0.4 120 85 4 Min 2.0 Typ Max 3.6 0.8 Unit V V V V A mA pF IOH = -20mA1 IOL = 20mA1 Note 2. Condition Cpd Power Dissipation Capacitance 25 pF Per Output 1. The MPC946 outputs can drive series or parallel terminated 50 (or 50 to VCC/2) transmission lines on the incident edge (see Applications Info section). 2. IIN current is a result of internal pull-up/pull-down resistors. AC CHARACTERISTICS (TA = 0 to 70C, VCC = 3.3V 0.3V) Symbol Fmax tPLH, tPHL tsk(o) Characteristic Maximum Input Frequency Propagation Delay TCLK to Q Min 150 5.0 4.5 8.0 7.5 12.0 11.5 350 350 350 450 2.0 3 3 0.1 0.5 4.5 11 11 1.0 ns ns ns ns Typ Max Unit MHz ns ps Condition Note 1. Note 1., 3. Note 1., 3. Fmax < 100MHz Fmax < 100MHz Fmax > 100MHz Fmax > 100MHz Note 2. Note 3. Note 3. 0.8V to 2.0V, Note 3. Output-to-Output Skew Same Frequency Outputs Different Frequency Outputs Same Frequency Outputs Different Frequency Outputs Part-to-Part Skew Output Enable Time Output Disable Time tsk(pr) tPZL, tPZH tPLZ, tPHZ tr, tf Output Rise/Fall Time 1. Driving 50 transmission lines. 2. Part-to-part skew at a given temperature and voltage. 3. Termination is 50 to VCC/2. TIMING SOLUTIONS BR1333 -- Rev 6 3 MOTOROLA MPC946 APPLICATIONS INFORMATION Driving Transmission Lines The MPC946 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 10 the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to application note AN1091 in the Timing Solutions brochure (BR1333/D). In most high performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 resistance to VCC/2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC946 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 1 illustrates an output driving a single series terminated line vs two series terminated lines in parallel. When taken to its extreme the fanout of the MPC946 clock driver is effectively doubled due to its capability to drive multiple lines. line impedances. The voltage wave launched down the two lines will equal: VL = VS ( Zo / Rs + Ro +Zo) = 3.0 (25/53.5) = 1.40V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.8V. It will then increment towards the quiescent 3.0V in steps separated by one round trip delay (in this case 4.0ns). 3.0 OutA tD = 3.8956 OutB tD = 3.9386 2.5 VOLTAGE (V) 2.0 In 1.5 1.0 0.5 0 2 4 6 8 TIME (nS) 10 12 14 MPC946 OUTPUT BUFFER IN 7 RS = 43 ZO = 50 OutA Figure 2. Single versus Dual Waveforms Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 3 should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. MPC946 OUTPUT BUFFER 7 RS = 36 ZO = 50 MPC946 OUTPUT BUFFER IN 7 RS = 43 ZO = 50 OutB0 RS = 43 ZO = 50 OutB1 RS = 36 ZO = 50 Figure 1. Single versus Dual Transmission Lines The waveform plots of Figure 2 show the simulation results of an output driving a single line vs two lines. In both cases the drive capability of the MPC946 output buffers is more than sufficient to drive 50 transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC946. The output waveform in Figure 2 shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 43 series resistor plus the output impedance does not match the parallel combination of the 7 + 36 k 36 = 50 k 50 25 = 25 Figure 3. Optimized Dual Line Termination SPICE level output buffer models are available for engineers who want to simulate their specific interconnect schemes. In addition IV characteristics are in the process of being generated to support the other board level simulators in general use. MOTOROLA 4 TIMING SOLUTIONS BR1333 -- Rev 6 MPC946 OUTLINE DIMENSIONS FA SUFFIX TQFP PACKAGE CASE 873A-02 ISSUE A A A1 32 25 4X 0.20 (0.008) AB T-U Z 1 -T- B B1 8 -U- V P DETAIL Y 17 AE V1 AE DETAIL Y 9 -Z- 9 S1 S 4X 0.20 (0.008) AC T-U Z G -AB- SEATING PLANE DETAIL AD -AC- BASE METAL F 8X M_ R CE SECTION AE-AE X DETAIL AD TIMING SOLUTIONS BR1333 -- Rev 6 GAUGE PLANE 0.250 (0.010) H W K Q_ 5 EE EE EE EE N D 0.20 (0.008) M AC T-U Z 0.10 (0.004) AC NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -AB-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.500 0.700 12_ REF 0.090 0.160 0.400 BSC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.020 0.028 12_ REF 0.004 0.006 0.016 BSC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF J DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X -T-, -U-, -Z- MOTOROLA MPC946 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405; Denver, Colorado 80217. 303-675-2140 or 1-800-441-2447 MfaxTM: RMFAX0@email.sps.mot.com - TOUCHTONE 602-244-6609 INTERNET: http://www.mot.com/sps/ JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 81-3-3521-8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 MOTOROLA 6 *MPC946/D* MPC946/D TIMING SOLUTIONS BR1333 -- Rev 6 |
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